The present invention relates to telecommunications in general, and, more particularly, to an apparatus for converting a serialized stream of bits into parallel words.
There are situations where parallel words of bits need to be transmitted via a serial communications channel. In these situations, a first apparatus converts the words into a serialized stream of bits for transmission on the serial communications channel. Typically the first apparatus is known as a serializer.
At the receiving end of the serial communications channel, a second apparatus captures the serialized stream of bits and restores it back into parallel words. Typically, the second apparatus is known as a deserializer. Regardless of what the first apparatus and the second apparatus are called, the second apparatus performs the inverse operation of the first apparatus.
FIG. 1 depicts a block diagram of serial communications system 100 in the prior art, which comprises: serializer 101, deserializer 102, timing source 103, timing source 104, and serial communications channel 111, interconnected as shown.
Serializer 101 receives a parallel word of bits and a clock signal (e.g., a clock signal, etc.) from timing source 103 and converts the parallel word into a serialized stream of bits for transmission via serial communications channel 111. For example, serializer 101 can comprise a parallel-load-in/serial-shift-out register that loads words in at a slower rate than it shifts bits out.
Serial communications channel 111 is a logical data structure that can be carried alone or can be multiplexed with other serial communications channels, via a metal wireline, an optical fiber, or a wireless channel (e.g., radio, infrared, etc.).
Deserializer 102 receives the serialized stream of bits from serial communications channel 111 and a clock signal from timing source 104, captures the serialized stream of bits, and converts it back into a parallel word. For example, deserializer 102 can comprise a serial-shift-in/parallel-unload-out shift register that unloads words more slowly than it shifts bits in.
The design and operation of deserializer 102 can be problematic. For example, if deserializer 102 samples the serialized stream of bits at the right time (i.e., when each bit in the serialized stream of bits is stable) deserializer 102 will capture a genuine bit that represents a valid value. In contrast, if deserializer 102 samples the serialized stream of bits at the wrong time (i.e., when some or all of the bits in the serialized stream of bits is in transition) deserializer 102 will capture a spurious bit that represents a false value. Furthermore, deserializer 102 might be incapable of distinguishing between when it is capturing genuine bits and when it is capturing spurious bits.
The design and operation of deserializer 102 is particularly problematic when: (1) timing source 103 is asynchronous to timing source 104, and (2) when timing source 104 is asynchronous to the transitions in the serialized stream of bits.
One common approach to this problem in the prior art is to greatly oversample the serialized stream of bits with the knowledge that by doing so the intervals of stability can be distinguished from the intervals of transition.
Another common approach to this problem in the prior art is to employ a phase-locked loop in the deserializer to sense when the transitions occur in the serialized stream of bits.
These approaches have well-known disadvantages, however, and, therefore, the need exists for a deserializer without some of the costs and disadvantages of deserializers in the prior art.
Some embodiments of the present invention enable the deserialization of one or more serialized streams of bits without some of the costs and disadvantages for doing so in the prior art. For example, the illustrative embodiment of the present invention incorporates a detection and feedback mechanism for ensuring that the deserializer samples each serialized stream of bits at the right time. In other words, the illustrative embodiment automatically detects when to sample a serialized stream of bits and adjusts that time, if necessary, to compensate for variations (e.g., jitter, wander, etc.) in either: (i) the transitions of the serialized stream of bits, or (ii) the timing source of the deserializer, or (iii) both the transitions of the serialized stream of bits and the timing source of the deserializer.
Furthermore, embodiments of the present invention can be used to parallelize a serial stream of bits that have not previously existed in parallel. In other words, equipment exists that originally generates one or more serial streams of bits, and the illustrative embodiment can be used to parallelize those serial streams of bits even though they have never previously existed in parallel.
And still furthermore, the illustrative embodiment of the present invention can operate at a frequency that is below the bit rate of the serialized stream of bits. This can be advantageous for several reasons.
First, the illustrative embodiment enables a device to capture a serialized stream of bits with a bit rate that is higher than the rate at which the device itself can operate. For example, the illustrative embodiment enables an integrated circuit technology that can operate at up to 300 MHz to capture a serialized stream of bits with a 3000 Mbs bit rate.
Second, the illustrative embodiment enables a device with a low-frequency timing source to capture a serialized stream of bits with a high bit rate. This is advantageous because a low-frequency timing source is often less expensive and more stable than a high-frequency timing source.
Third, the illustrative embodiment enables a device to operate at a low clock rate and yet to capture a serialized stream of bits with a high bit rate. This is advantageous because a device that operates at a low clock rate can use less power (i.e., wattage) than a gate equivalent circuit that operates at a higher clock rate.
And fourth, the illustrative embodiment enables a device to avoid deriving or modifying its clock signal from the serialized stream of bits, which eliminates the possibility that jitter in the serialized stream of bits can pollute the clock signal of the deserializer.
The illustrative embodiment comprises: a first bi-stable storage device for receiving a first binary waveform and a first clock signal and for generating a second binary waveform based on the first binary waveform and on the first clock signal; a second bi-stable storage device for receiving the first binary waveform and a second clock signal and for generating a third binary waveform based on the first binary waveform and on the second clock signal; and unanimity logic for generating a fourth binary waveform based on a coincidence function of the second binary waveform and the third binary waveform.